200+ Trắc nghiệm Thiết kế hệ thống số dùng HDL (có đáp án)

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Tổng hợp trên 200 câu hỏi trắc nghiệm Thiết kế hệ thống số dùng HDL có đáp án với các câu hỏi đa dạng, phong phú từ nhiều nguồn giúp sinh viên ôn trắc nghiệm Thiết kế hệ thống số dùng HDL đạt kết quả cao.

200+ Trắc nghiệm Thiết kế hệ thống số dùng HDL (có đáp án)

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Quảng cáo

Câu 1: Which of the following statements are true? (multiple choices)

A. All of the above

B. A variable index used at the RHS of an “assign” statement generates a multiplexer whereas usage of it at the LHS results in a decoder

C. The “assign” statement can be used to implement both combinational as well as sequential circuits

D. The use of conditional operator in an “assign” statement always results in a multiplexer

Câu 2: Which is not a correct method of specifying time scale in verilog?

A. 100ns/110ps

B. 1ns/1ps

C. 100ns/100ps

D. 10ns/1ps

Quảng cáo

Câu 3: The task $stop is provided to

A. None of the above

B. Suspend simulation

C. End simulation

D. Exit simulator

Câu 4: If “clk” and “clear” are two inputs of a counter module, which of the following event expressions must be used if we want to implement asynchronous clear (assuming “clear” is active low, active high edge of “clk” signal is used for counting, and single “always” block is used for the implementation)?

A. always @(negedge clear)

B. always @(posedge clk or negedge clear)

C. always @(posedge clk)

D. None of these

Câu 5: For the following code segment, the final value of variable “d” will be …

Quảng cáo

integer a, b, c, d;

initial begin

  a = 25;

  b = 12;

  c = 5;

  d = 17;

  a = b + c;

  b = a – 15;

  c = a + d;

  d = c + d;

end

A. 58

B. 51

C. 40

D. 53

Câu 6: Which of the following is true for the following module?

module mydesign (a,b);

input [1:0] b;

output reg a;

always @(b)

   begin

      if (b==2'b00) a = 1'b0;

      else if (b==2'b11) a = 1'b0;

      else a = 1'b1;

   end

end module

A. A latch will be generated for the output "a"

B. The synthesis tool will give an error

C. A combinational circuit implementing an AND function will be generated

D. A combinational circuit implementing a XOR function will be generated

Câu 7: Which of the following statements is/are true? (multiple choices)

A. The “assign” statement implements continuous assignment between the expression specified on the right-hand side and a “net” type variable specified on the left-hand side

B. The “assign” statement implements continuous assignment between the expression specified on the right-hand side and a “reg” type variable specified on the left-hand side

C. None of these

D. The “assign” statement can be used to model a latch, which is a sequential circuit

Quảng cáo

Câu 8: If A = 4b011 and B = 4b0011, then the result of A ** B will be

A. 9

B. Invalid expression

C. 6

D. 27

Câu 9: The following code segment generates a periodic clock signal “clk” with time period:

initial clk = 1’b1;

always #10 clk = ~clk;

A. None of these

B. 10

C. 20

D. 30

Câu 10: What does the following code segment indicate?

initial clk = 1’b0;

always #5 clk = ~clk;

A. Raising edges of the clock will appear at times 5, 15, 25, 35, …

B. Raising edges of the clock will appear at times 5, 10, 15, 20, …

C. None of the above

D. Raising edges of the clock will appear at times 10, 20, 30, 40, …

Câu 11: Which of the following is true for the module given below?

module mydesign (a,b,c);

input c;

output reg a, b;

always @(c)

begin

   if (c == 1’b0)

   begin

      b <= ~a;

      a <= ~(c | b);

   end

   else if (c == 1’b1)

      a <= ~(b ^ c);

end

endmodule

(multiple choices)

A. The synthesis tool will give an error

B. A pure combinational circuit using NOT, NOR, and XNOR logic gates will be implemented

C. A latch with enable signal c will be generated for the output b

D. A 2-to-1 multiplexer will be generated

Câu 12: Which of the following is true about the following code segment?

integer x, y;

initial

begin

  x = 15;

  y = 10;

end

initial

  repeat (x) $display (“x=%d”, x);

initial

  while (y < 12)

  begin

    y = y + 1;

    x = x - 1;

  end

A. It cannot be determined exactly how many times the value of ‘x’ will be printed

B. The simulation will print the current value of ‘x’ 15-times

C. The simulation will print the current value of ‘x’ 13-times

D. The simulation will always display 15 as the value of ‘x’

Câu 13: Consider the following Verilog module.

module guess (data, cond, result);

input [7:0] data;

input [1:0] cond;

output reg result;

always @(data)

begin

   if (cond == 2’b00)

      result = |data;

   else

      result = ~^data;

end

endmodule

Which of the following are true when the module is synthesized? (multiple choices)

A. The synthesize system will generate a wire for result

B. A combinational circuit will be generated

C. None of the above

D. A sequential circuit with a storage element for result will be generated

Câu 14: What will the following code segment generate on synthesis, assuming that the four variables data0, data1, data2 and data3 map into four latches/flip-flops?

always @(posedge clock)

begin

  data3 = din;

  data2 = data3;

  data1 = data2;

  data0 = data1;

end

A. None of these

B. A 4-bit parallel-in parallel-out register

C. A 4-bit shift register

D. Four D flip-flops all fed with the data “din”

Câu 14 (Phần 2): If A = 4b001x and B = 4b1011, then result of A + B will be

A. 110x

B. 1100

C. xxxx

D. None of the above

Câu 15: What will the following code segment do?

always @(posedge clock)

begin

    y = x;

    z = y;

    x = z;

end

A. All the variables will get the value previously stored in “z”

B. Shift the values stored in the three variables

C. All the variables will get the value previously stored in “y”

D. All the variables will get the value previously stored in “x”

Câu 16: What does the construct “#5” indicate in simulation?

A. It specifies that the unit of delay is 5 nanoseconds

B. It pauses execution of the statements that follow after time 5

C. It schedules the execution of the next statement at time 5

D. It specifies a delay of 5 time units before executing the next statement

Câu 17: Which of the following is true for the “repeat” loop?

A. None of these

B. It can be used to iterate a block indefinitely

C. It can be used to repeat execution of the block exactly two times

D. It can be used to iterate a block until a specified condition is true

Câu 18: For the following Verilog code segment:

wire [7:0] A;

wire B;

assign B = ~|A;

If the value of A is 8’b00111001, what will be the value of {A[5:3], 3{B}}?

A. 6’b111000

B. 6’b011000

C. None of the above

D. 6’b111111

Câu 19: If A, B, C and D are reg, reg, integer and wire variables respectively, each of size [7:0], which of the following is/are allowed inside a procedural block? (Multiple choice)

A. D = C + 1;

B. B[3:0] = D[4:1] + 1;

C. D = A + B;

D. C = A + D;

Câu 20: Consider the following Verilog code segment:

wire [5:0] A, B;

wire C;

assign C=^A;

If the values of A and B are 5’b10011 and 5’b01110 respectively, what will be the value of {A[3:1], 2{C}, B[2:0]}?

A. 00100110

B. 00111110

C. 01111110

D. None of these

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